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Espressif Systems /ESP32-C6 /UHCI0 /CONF1

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Interpret as CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHECK_SUM_EN)CHECK_SUM_EN 0 (CHECK_SEQ_EN)CHECK_SEQ_EN 0 (CRC_DISABLE)CRC_DISABLE 0 (SAVE_HEAD)SAVE_HEAD 0 (TX_CHECK_SUM_RE)TX_CHECK_SUM_RE 0 (TX_ACK_NUM_RE)TX_ACK_NUM_RE 0 (WAIT_SW_START)WAIT_SW_START 0 (SW_START)SW_START

Description

UHCI Configuration Register1

Fields

CHECK_SUM_EN

Set this bit to enable head checksum check when receiving.
CHECK_SEQ_EN

Set this bit to enable sequence number check when receiving.
CRC_DISABLE

Set this bit to support CRC calculation, and data integrity check bit should 1.
SAVE_HEAD

Set this bit to save data packet head when UHCI receive data.
TX_CHECK_SUM_RE

Set this bit to encode data packet with checksum.
TX_ACK_NUM_RE

Set this bit to encode data packet with ACK when reliable data packet is ready.
WAIT_SW_START

Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
SW_START

Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd